When bonding two DDR3 hard memory controllers in Cyclone® V or Arria® V, you may experience timing violations on the bonding interface. These violations are valid. The workaround is to insert pipeline registers for the bonding signals.Are the timing violations on the bonding interface of my Cyclone® V or Arria® V DDR3 bonded hard memory controller design valid?
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在 Cyclone® V 或 Arria® V 中綁定兩個 DDR3 硬記憶體控制器時，您可能會在綁定介面上遇到時序衝突。這些違規行為是有效的。
解決方法是為綁定信號插入管道寄存器。